A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC

Optical on-chip interconnects and 3D die stacking are currently considered to be two promising paradigms for the design of next generation Multi-Processors System on Chip architectures (MPSoC). New architectures based on these paradigms are currently emerging and new system-level approaches are required for their efficient design and prototype. The paper investigates a system-level flow for evaluating design feasibility, interconnect architecture performance and application execution efficiency as early as possible in the MPSoC design cycle.