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DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current

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3 Author(s)
Yu Sun ; Microelectron. Center, Harbin Inst. of Technol., Harbin, China ; Li-yi Xiao ; Cong Shi

Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010