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Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications

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2 Author(s)
W. C. H. Lin ; Dept of Electrical Engineering, BL-528 National Taiwan University Taipei, Taiwan 106 ; J. B. Kuo

This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at a power supply voltage of 0.5V.

Published in:

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Date of Conference:

May 30 2010-June 2 2010