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A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages

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3 Author(s)
Young-Hwa Kim ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Jaewon Lee ; SeongHwan Cho

A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power hungry sample-and-hold amplifier can be removed and rail-to-rail input can be used. In addition, feedback factor of the first MDAC can be increased, which significantly reduces the power consumption of the first opamp. Simulation results in 90 nm CMOS show that 8.88 bits of effective-number-of-bits at 300 MHz sampling rate can be achieved while consuming 77mW at 1.2V supply. Figure-of-merit of the proposed ADC is 545fJ/Conv, which is one of the lowest among the recently reported ADCs that achieve 10-bit resolution with sampling rates of hundreds of mega-hertz.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010