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A high-bandwidth power-scalable 10-bit pipelined ADC utilizing a newly-proposed bandwidth-reconfigurable operational amplifier is presented and verified. The ADC accomplishes power-scalable functionality by altering the bias currents of the opamps in proportion to the ADC's sampling frequency without pushing the MOS transistors into a weak inversion regime. Post-layout simulation in a 1.2-V 65-nm CMOS process shows that power consumption is scaled from 21.4 mW (100 MS/s) to 9.8 mW (25 MS/s) while maintaining an SNDR higher than 58 dB over the entire sampling frequency range. The ADC achieves an FOM of 0.29 pJ/conversion-step for a sampling rate of 100 MS/s with an input signal frequency of 20.7 MHz.