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IP-cores design for the kNN classifier

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2 Author(s)
Manolakos, E.S. ; Dept. of Inf. & Telecommun., Univ. of Athens, Athens, Greece ; Stamoulias, I.

We present the systematic design of two linear array IP cores for the k-nearest neighbor (k-NN) benchmark classifier. The need for real-time classification of data vectors with possibly thousands of features (dimensions) motivates the implementation of this widely used algorithm in hardware in order to achieve very high performance by exploiting block pipelining and parallel processing. The two linear array architectures that we designed have been described as soft IP cores in fully parameterizable VHDL that can be used to synthesize effortlessly different k-NN parallel architectures for any desirable combination of the problem size parameters. They have been evaluated for a large variety of parameter combinations and Xilinx FPGAs. It is shown that they can be used to solve efficiently very large size k-NN classification problems, even with thousands of training vectors or vector dimensions, using a single, moderate size FPGA device. Furthermore the FPGA implementations exceed by a factor of two the performance of optimized NVIDIA CUDA API software implementations for the powerful GeForce 8800GTX GPU.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010