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High-speed and low-power programmable frequency divider

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5 Author(s)
Ting-Hsu Chien ; National Chip Implementation Center, Hsinchu, Taiwan ; Chi-Sheng Lin ; Chin-Long Wey ; Ying-Zong Juang
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This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using the TSMC 0.18 μm 1P6M CMOS process. With an 8-stage 2/3 divider cell, the measurement results indicate that the proposed circuit operates up to 5.8 GHz with the power-consumption less than 3.24 mW.

Published in:

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Date of Conference:

May 30 2010-June 2 2010