Skip to Main Content
In this paper we present a 1.6-GHz pipeline A/D converter (ADC) for digital television and digital broadcast satellite. The ADC, designed in a standard 65-nm CMOS technology, achieves in simulation a signal-to-noise and distortion ratio (SNDR) of 54.3 dB (8.73 ENOB), over a signal bandwidth of 615 MHz. The ADC core consumes 430 mW from 1-V and 2.5-V power supplies. In order to achieve the required sampling frequency, the proposed ADC exploits a time-interleaved architecture with four paths. Each path consists of a 10-bit pipeline ADC with four stages (a 3.5-bit stage, a 1.5-bit stage, a 2.5-bit stage and a final 4-bit flash stage). Operational amplifier sharing is adopted in the last two stages for reducing the power consumption. The active area of the chip is 2.7 × 3.2 mm2.
Date of Conference: May 30 2010-June 2 2010