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A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS technology with a nominal power supply VDD of 1.5 V and a negative voltage of -4.5 V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 62% and 65%, respectively. In addition, the proposed level shifter realizes a wide operation margin with a lower VDD compared to conventional implementations.
Date of Conference: May 30 2010-June 2 2010