Referenced Items are not available for this document.
This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.
Published in:
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Date of Conference: May 30 2010-June 2 2010
- Page(s):
- 925 - 928
- E-ISBN :
- 978-1-4244-5309-2
- Print ISBN:
- 978-1-4244-5308-5
- INSPEC Accession Number:
- 11462621
- Conference Location :
- Paris
- Digital Object Identifier :
- 10.1109/ISCAS.2010.5537402
- Product Type:
- Conference Publications
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