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Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

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4 Author(s)
Akira Ohchi ; Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan ; Nozomu Togawa ; Masao Yanagisawa ; Tatsuo Ohtsuki

In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

Published in:

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Date of Conference:

May 30 2010-June 2 2010