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A multiple code-rate turbo decoder based on reciprocal dual trellis architecture

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3 Author(s)
Chen-Yang Lin ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Cheng-Chi Wong ; Chang, Hsie-Chia

To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010

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