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Asynchronous FPGA architecture with distributed control

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3 Author(s)
Delong Shang ; MSD Group, Newcastle Univ., Newcastle upon Tyne, UK ; Xia, F. ; Yakovlev, A.

Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possible, whilst achieving delay insensitivity in the inter-cell interconnects. By using David Cells as the central technique in the delay insensitive clock replacement, this method is conducive to the establishment of an automatic design and synthesis flow. It also particularly caters for low power designs, where current FPGA solutions are not effective yet.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010