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Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

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6 Author(s)
Tongsheng Geng ; Research Center for Mobile Computing, Tsinghua University, Institute of microelectronics, Tsinghua University, Tsinghua National Laboratory for Information Science and Technology, Beijing, 100084, China ; Leibo Liu ; Shouyi Yin ; Min Zhu
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Computing-intensive algorithms which occupy most of executing time are always the main bottleneck in real-time or high quality video applications. In this paper, the optimization methods of the computing-intensive decoding algorithms of H.264, including MC (Motion Compensation), Deblocking and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization), are proposed firstly, and then implemented on the REMUS (REconfigurable MUltimedia System) which is an embedded coarse-grain reconfigurable multimedia system. Tests show that the efficiency of MC is improved by 32.5%, Deblocking by 69% and IDCT-IQ by 88.5% compared with XPP PACT(a commercial reconfigurable processor). Compared with typical ASIC solutions, execution performance of MC and IDCT improved by 49% and 17%, respectively, while that of Deblocking remained about the same.

Published in:

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Date of Conference:

May 30 2010-June 2 2010