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The verification of mixed-signal SoC is emerging as the most significant challenge, and with its cost surpassing the chip design cost. This paper presents a new automated verification methodology namely RVM (recursively verifying and modeling) and a set of supporting electronic design automation tools. The RVM methodology is built on the existing design flow and environments but with three major innovations to cope with custom-designed transistor blocks: a tool for automatically generating and validating simulation-efficiently behavioral models from a circuit netlist, a tool for characterizing and verifying the electrical rule correctness of analog blocks, and a hierarchical environment that allows designers to control the modeling and verification complexity. With the RVM methodology, analog circuits are verified in a way similar to the well-established digital verification. A set of industry benchmark results have shown that the RVM methodology is cable of reducing the verification time by potentially 100× to 1000×. With the increasing complexity of full-chip mixed-signal system-on-chip design, the RVM methodology is emerging as the only scalable verification solution.