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Non-DVFS dynamic thermal management (DTM) techniques like fetch-throttling, rename-throttling and register-file occupancy-throttling have some favorable features compared to dynamic voltage and frequency scaling (DVFS) technique for the potential use in multi-core chip designs. This paper presents an approach to implement these non-DVFS techniques in a processor architecture. This analysis and implementation provides a way to evaluate the performance of these DTM techniques in multi-core chips and resolve some implementation restrictions. The combination of CPU and memory bound workloads are used to simulate the proposed implementation. The observations are verified by using RTL level simulations in Verilog for power estimation and fuctionality check.