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Minimum spanning tree (MST) computation on a general graph is an irregular algorithm. Regular, data-parallel algorithms map well to the SIMD architecture of cell BE. Irregular algorithms on discrete structures like graphs are harder to map to them. Obtaining efficient parallel implementations for irregular graph problems always remains a challenge. The contribution of this paper lies in presenting a parallel implementation of MST on multi-core Cell Broadband Engine Architecture by utilizing the cell architecture potentials including DMA transfer, double buffering, mailboxes and at the same time considering the architecture limitations including memory constrains and thread synchronization. The implementation achieves up to 7 times speedup over sequential implementation.
Date of Conference: 20-21 June 2010