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A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

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4 Author(s)
Shyh-Jye Jou, ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Chang-Yu Chen ; En-Chung Yang ; Chau-Chin Su

This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 1 )

Date of Publication:

Jan 1997

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