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An eight-bit prefetch circuit for high-bandwidth DRAM's

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5 Author(s)
Sunaga, T. ; Semicond. Technol. Dev., IBM Japan Ltd., Shiga-ken, Japan ; Hosokawa, K. ; Nakamura, Y. ; Ichinose, M.
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A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm2 is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M×16-b configuration dissipates 60 mA at 3.6 V

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 1 )

Date of Publication:

Jan 1997

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