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A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

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4 Author(s)
B. W. McGaughy ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; J. C. Chen ; D. Sylvester ; Chenming Hu

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF.

Published in:

IEEE Electron Device Letters  (Volume:18 ,  Issue: 1 )