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Self-aligned offset gated poly-Si TFTs with a floating sub-gate

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5 Author(s)
Park, Cheol-Min ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Byung-Hyuk Min ; Jun, Jae-Hong ; Yoo, Juhn-Suk
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We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained.

Published in:

Electron Device Letters, IEEE  (Volume:18 ,  Issue: 1 )