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A multi-story power delivery technique for 3D integrated circuits

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4 Author(s)
Jain, P. ; Dept of ECE, Univ. of Minnesota, Minneapolis, MN, USA ; Tae-Hyoung Kim ; Keane, J. ; Kim, C.H.

Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.

Published in:

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date of Conference:

11-13 Aug. 2008