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Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power

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2 Author(s)
Koustav Bhattacharya ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Nagarajan Ranganathan

The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we develop a first order model of the soft error phenomenon in logic circuits and incorporate power and delay metrics to formulate a convex programming based reliability-centric gate sizing technique. The proposed algorithm has been implemented and validated on the ISCASS85 benchmarks. Experimental results indicate that our multi-objective optimization technique can achieve significant reductions in soft error rate with simultaneous optimization of delay and power.

Published in:

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date of Conference:

11-13 Aug. 2008