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Full-system chip multiprocessor power evaluations using FPGA-based emulation

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3 Author(s)
Abhishek Bhattacharjee ; Dept. of Electr. Eng., Princeton Univ., Princeton, NJ, USA ; Gilberto Contreras ; Margaret Martonosi

The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.

Published in:

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date of Conference:

11-13 Aug. 2008