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A fine-grain multithreading superscalar architecture

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2 Author(s)
M. Loikkanen ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; N. Bagherzadeh

In this study we show that fine-grain multithreading is an effective way to increase instruction-level parallelism and hide the latencies of long-latency operations in a superscalar processor. The effects of long-latency operations, such as remote memory references, cache-misses, and multi-cycle floating-point calculations, are detrimental to performance since such operations typically cause a stall. Even superscalar processors, that are capable of performing various operations in parallel, are vulnerable. A fine-grain multithreading paradigm and unique multithreaded superscalar architecture is presented. Simulation results show significant speedup over single-threaded superscalar execution

Published in:

Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on

Date of Conference:

Oct 1996