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Design automation of digital circuits for partially depleted SOI-technology

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2 Author(s)
A. Sikora ; Fraunhofer Inst. fur Mikroelektron. Schaltungen & Syst., Duisburg, Germany ; H. -L. Fielder

This paper shows that it is possible to adapt commercially available layout generators to the specific needs of partially depleted (PD)-SOI-technologies with minimal area penalty. Therefore, the requirements of SOI-specific layout techniques are investigated. A design flow for automatic layout generation is proposed. An implementation is presented with a cell library created with this generator. Measurements of test circuitry at temperatures up to 390 °C and supply voltages up to 10 V are shown

Published in:

SOI Conference, 1996. Proceedings., 1996 IEEE International

Date of Conference:

30 Sep-3 Oct 1996