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Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 μm

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8 Author(s)
J. A. Burns ; Lincoln Lab., MIT, Lexington, MA, USA ; C. L. Keast ; J. M. Knecht ; R. R. Kunz
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Lincoln Laboratory has developed a fully-depleted silicon-on-insulator (SOI) technology to build integrated circuits designed for very low power operation and fabricated at the limits of optical lithography. A 0.25 μm (drawn gate length) fully-depleted SOI CMOS process technology was established using 248-nm optical lithography for initial process demonstrations, and to identify nonlithographic process integration pinch points and SOI material related issues. Design rules and SPICE parameters have been issued for the 0.25 μm technology and a multi-project chip set assembled. The process technology has been adapted to Lincoln's 193-nm step-and-scan tool to fabricate O.2 μm circuits and provide the first application of 193-nm lithography to a complete CMOS process. This paper describes the performance characteristics of the technology and the enhancements necessary to extend it to 0.15 μm

Published in:

SOI Conference, 1996. Proceedings., 1996 IEEE International

Date of Conference:

30 Sep-3 Oct 1996