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Sub-0.25 μm ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

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8 Author(s)
Raynaud, C. ; CEA, Centre d''Etudes Nucleaires de Grenoble, France ; Faynot, O. ; Pelloie, J.L. ; Tedesco, S.
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Fully-depleted (FD) 0.2 μm SOI CMOS devices have been fabricated with a single N+ gate process. As an ultra-thin film is required to optimize fully-depleted 0.2 μm SOI devices, a recessed channel structure has been used in order to prevent any contact problems. Dynamic performance has been demonstrated down to 1 V supply voltage with 0.25 μm ring oscillators (propagation delay of 80 ps at 1.5 V) and 0.2 μm 16 K SRAM (access time of 6 ns at 1.5 V). These results show that 0.2 μm FD SOI devices meet the requirements for low voltage and low power applications

Published in:

SOI Conference, 1996. Proceedings., 1996 IEEE International

Date of Conference:

30 Sep-3 Oct 1996