Cart (Loading....) | Create Account
Close category search window
 

Controller design for tracking induced miss-rates in cache memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Almoosa, N. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Wardi, Y. ; Yalamanchili, S.

Cache systems are on-chip memory elements used to store data that are frequently referenced by programs. The advantage of storing data in cache, as compared to RAM, is that it has faster retrieval times, but it has the disadvantage of on-chip energy consumption. A cache-decay interval is the amount of time a cache element holds unreferenced data before being turned off (cleared). The choice of a cache-decay interval comprises a balance between low energy consumption and low induced miss rates. In certain applications this balance is determined off line by computing the cache-decay interval that would yield a given level of induced miss rates. However, the lack of precise models, coupled with program-dependent behavior of the cache system, result in possibly-drastic fluctuations in the induced miss rates for a given decay interval. This paper presents a control system designed to track a given reference of induced miss rates by recomputing (in real time) the decay interval. Simulation studies indicate that the plant can be approximated adequately by a power function. The controller's design is carried out in the log domain, where the system is linear but subjected to an unknown output disturbance. We propose an integral controller and perform its stability analysis. Simulation studies on Simplescalar, a microprocessor simulator, testify to the efficacy of our proposed approach and appear to yield tighter bounds than those derived to-date by other means.

Published in:

Control and Automation (ICCA), 2010 8th IEEE International Conference on

Date of Conference:

9-11 June 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.