By Topic

Survey of low power techniques for VLSI design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
de Angel, E. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Swartzlander, E.E.

This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 μm technology and simulated in PowerMill

Published in:

Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on

Date of Conference:

9-11 Oct 1996