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Survey of low power techniques for VLSI design

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2 Author(s)
E. De Angel ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; E. E. Swartzlander

This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 μm technology and simulated in PowerMill

Published in:

Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on

Date of Conference:

9-11 Oct 1996