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This paper addresses the problem of finding the right system prototyping hardware which can handle all different kinds of routing graphs for various designs and applications. A structure of multiple field-programmable gate arrays (FPGAs) and their concentric arrangement is proposed. The connectivity is switch based and has no routing limitation. Therefore, no routing limitations must be considered during the design partitioning process. The delays between FPGA pins are short compared to alternative concepts and can be considered as equal. This equal length concept between FPGA pins enables a novel method of wave-pipelined multiplexed data transfer. The flexible routing, the short delays and the equal length aspect enable faster system speeds compared to alternative concepts. The predictive and constant delay between FPGAs eases board level timing models for timing driven system partitioning algorithms.