By Topic

Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Tobias Strauch ; R&D, EDAptability e.K., Munich, Bavaria, Germany

This paper addresses the problem of finding the right system prototyping hardware which can handle all different kinds of routing graphs for various designs and applications. A structure of multiple field-programmable gate arrays (FPGAs) and their concentric arrangement is proposed. The connectivity is switch based and has no routing limitation. Therefore, no routing limitations must be considered during the design partitioning process. The delays between FPGA pins are short compared to alternative concepts and can be considered as equal. This equal length concept between FPGA pins enables a novel method of wave-pipelined multiplexed data transfer. The flexible routing, the short delays and the equal length aspect enable faster system speeds compared to alternative concepts. The predictive and constant delay between FPGAs eases board level timing models for timing driven system partitioning algorithms.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 9 )