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Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA.
Date of Publication: Oct. 2010