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With the increasing popularity of multi-core processors and the promise of future many-core systems, parallel CAD algorithm development has attracted a significant amount of research effort. However, a highly relevant issue, parallel program performance modeling has received little attention in the EDA community. Performance modeling serves the critical role of guiding parallel algorithm design and provides a basis for runtime performance optimization. We propose a systematic composable approach for the performance modeling of a recently developed hierarchical multi-algorithm parallel circuit simulation (HMAPS) approach. The unique integration of inter- and intra-algorithm parallelisms allows a multiplicity of parallelisms to be exploited in HMAPS and also creates interesting modeling challenges in forms of complex performance tradeoffs and large runtime configuration space. We model the performances of key subtask entities as functions of workload and parallelism. We address significant complications introduced by inter-algorithm interactions in terms of memory contention and collaborative simulation behavior via novel penalty and statistical based modeling. The proposed approach is able to accurately predict the parallel performance of a given HMAPS configuration and hence enables the runtime optimization of the parallel simulation code.
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Date of Conference: 13-18 June 2010