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ACES: Application-specific cycle elimination and splitting for deadlock-free routing on irregular Network-on-Chip

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3 Author(s)
Cong, J. ; Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA ; Chunyue Liu ; Reinman, G.

Application-specific Network-on-Chip (NoC) in MPSoC designs often requires irregular topology to optimize power and performance. However, efficient deadlock-free routing, which avoids restricting critical routes and also does not significantly increase power for irregular NoC, has remained an open problem until now. In this paper an application-specific cycle elimination and splitting (ACES) method is presented for this problem. Based on the application-specific communication patterns, we propose a scalable algorithm using global optimization to eliminate as much channel dependency cycles as possible while ensuring shortest paths between heavily communicated nodes, and split only the remaining small set of cycles (if any). Experimental results show that compared to prior work, ACES can either reduce the NoC power by 11%~35% while maintaining approximately the same network performance, or improve the network performance by 10%~36% with slight NoC power overhead (-5%~7%) on a wide range of examples.

Published in:

Design Automation Conference (DAC), 2010 47th ACM/IEEE

Date of Conference:

13-18 June 2010