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Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

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4 Author(s)
Kalisz, J. ; Mil. Univ. of Technol., Warsaw, Poland ; Szplet, R. ; Pasierbinski, J. ; Poniecki, A.

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in “1-out-of-N” code and then converted to 6-bit natural binary. Within the temperature range from 0°C to 45°C, the time offset at the output is constant, the resolution changes by ±0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:46 ,  Issue: 1 )

Date of Publication:

Feb 1997

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