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Charge-based fault simulation for CMOS network breaks

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3 Author(s)
Konuk, H. ; California Design Center, Hewlett-Packard Co., Palo Alto, CA, USA ; Ferguson, F.J. ; Larrabee, T.

We define a network break as a break fault in the p-network or in the n-network of a CMOS cell that breaks one or more transistor paths between the cell output and Vdd or GND. Previous work, mostly in the context of transistor stuck-open faults, studied test invalidation due to transient paths to Vdd or GND, and due to charge sharing. In this paper we show the importance of Miller feedthrough and feedback capacitances in network break test invalidation, which was ignored by previous work. We present a new fault simulation algorithm for network breaks, with the following novelties: First, the electrical charge coming from Miller and p-n junction capacitances is computed using a transistor charge model; this automatically handles the nonlinear nature of transistor capacitances accurately, as opposed to assuming constant capacitance values as was done in previous work. Next, we use only six voltage levels for charge computations, which allows us to create look-up tables that dramatically reduce the computation time. Finally, the maximum voltage an internal node in an n-network can acquire is about three-fourths of the Vdd voltage (instead of Vdd as assumed by previous work), and similarly, a p-network node cannot discharge all the way down to the GND voltage. Using our simulator to analyze test sets for the ISCAS'85 circuits, we found that the charge coming from Miller capacitances has a larger share in test invalidation than the charge from p-n junction capacitances. Our simulator spends less time for charge computations than it spends for transient path identification

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 12 )

Date of Publication:

Dec 1996

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