Bit-parallel multidelay simulation

The multidelay parallel (MDP) technique is a multidelay logic simulation algorithm that uses no timing wheel, or any other event-sorting mechanism. Instead, wide bit-fields containing net-values for several different times are used to resolve out-of-order events. Bit-parallel operations are performed to simulate gates at the required times. The MDP technique was originally designed to be implemented in hardware, but the current software version of the algorithm has proven to be competitive with conventional event-driven multidelay simulation. Two versions of the MDP technique are presented in this paper, fixed alignment and variable alignment. The fixed alignment algorithm provides bit-fields that are wide enough to capture any event that could occur during the simulation of an input vector, while the variable alignment algorithm uses a minimum-width bit field which is just wide enough to capture those events that could occur at an individual step in the simulation. A prototype hardware design is discussed briefly.