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Increased process variations in nano-scaled technologies lead to parametric failures in embedded SRAMs. The reduction of the supply voltage in order to ensure low leakage power leads to a decrease in robustness. These are the main factors which affect the failure probability and so the circuit yield. A widely used technique to determine the failure probability is the full Monte Carlo simulation. However, in order to achieve high accuracy, the number of simulations must be extremely large making this procedure very expensive time wise. In this paper, a method for fast and accurate estimation of the failure probability is proposed. The method can be applied with a set of performance or response functions, and throughout this paper the Static Noise Margin metric is used.