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Optimal circuit design for low power CMOS GSI

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4 Author(s)
Bhavnagarwala, A.J. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; De, V.K. ; Austin, B. ; Meindl, J.D.

For a prescribed system performance, device, circuit and system design of a static CMOS datapath are conjointly optimized for different operating temperature ranges. Total power dissipation is reduced to one-third the value projected for 0.25 micron CMOS by the National Technology Roadmap for Semiconductors for a single datapath and to less than one-fourteenth the value projected for parallel datapaths assuming operation over a temperature range of 60°K above room temperature

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996