Referenced Items are not available for this document.
A low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level
Published in:
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Date of Conference: 23-27 Sep 1996
- Page(s):
- 291 - 294
- Meeting Date :
- 23 Sep 1996-27 Sep 1996
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-3302-0
- INSPEC Accession Number:
- 5472762
- Conference Location :
- Rochester, NY
- Digital Object Identifier :
- 10.1109/ASIC.1996.552013
- Product Type:
- Conference Publications
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