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An efficient path-delay fault simulator for mixed level circuits

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3 Author(s)
Yong Seok Kang ; Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea ; Yong Tae Yim ; Sungho Kang

This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996