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A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

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4 Author(s)
Eble, J.C. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; De, V.K. ; Wills, D.S. ; Meindl, J.D.

GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996