By Topic

Multichip module placement with heat consideration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Man Chak Tang ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; J. D. Carothers

A new algorithm for multichip module placement, MPH, using a combined quad-partitioning, genetic search and simulated annealing approach is presented here. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. The proposed algorithm obtains better solutions in less time than the simulated annealing and min-cut algorithms on the MCC industrial multichip module (MCM) benchmarks. In addition to the MCC benchmarks, industrial benchmarks for macrocell placement are used for testing the general placement power of the MPH algorithm. Results of these test cases are also presented

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996