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Multichip module placement with heat consideration

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2 Author(s)
Man Chak Tang ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; Carothers, J.D.

A new algorithm for multichip module placement, MPH, using a combined quad-partitioning, genetic search and simulated annealing approach is presented here. In addition to minimizing wire length and vias, the algorithm places chips so that heat is evenly distributed over the substrate. The proposed algorithm obtains better solutions in less time than the simulated annealing and min-cut algorithms on the MCC industrial multichip module (MCM) benchmarks. In addition to the MCC benchmarks, industrial benchmarks for macrocell placement are used for testing the general placement power of the MPH algorithm. Results of these test cases are also presented

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996