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SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts

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1 Author(s)
Gannett, J.W. ; VLSI Design Methodology Res. Group, Morristown, NJ, USA

Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. A description is given of an interactive CAD tool called Shortfinder that enables the user to find VLSI layout errors resulting in electrical shorts between complex nets quickly and with minimal effort. This is accomplished by displaying a cycle-free shortest electrical path between two points indicated by the user on a graphical display of the layout. Shortfinder was implemented as a modular enhancement to an existing layout viewing program; its data structures and algorithms are described

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 6 )