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Pixel cache architecture with FIFO implemented within an ASIC

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2 Author(s)
Ikedo, T. ; Comput. Archit. Lab., Aizu Univ., Japan ; Jianhua Ma

Implementation technology for 3D pixel cache and performance evaluation of a graphics processor Truga001, with 12 embedded processors within a single chip, are described. The chip can render 4 million vectors/s (10 pixels/vector) or 1.2 million triangle polygons/s (100 pixels/polygon) with Phong shading, texture mapping and hidden surface removal. A pixel-array configured with 8(x)×4(y)×24-bit(intensity)×24-bit(z) can be accessed with frame buffer at 180 ns due to the 3D bus-architecture between chip and frame buffer. The chip was designed with Toshiba TC180C CMOS of 400,000 gates

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996