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DVLASIC: catastrophic fault yield simulation in a distributed processing environment

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2 Author(s)
D. M. H. Walker ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; D. S. Nydick

Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, DVLASIC, the distributed-environment version developed by the authors, achieves a speedup of 13.3 over VLASIC, with an efficiency of 89%. The authors describe the distributed processing environment and implementation techniques used to obtain this speedup. The distributed processing environment can also be applied to many other CAD problems

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 6 )