Referenced Items are not available for this document.
Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, DVLASIC, the distributed-environment version developed by the authors, achieves a speedup of 13.3 over VLASIC, with an efficiency of 89%. The authors describe the distributed processing environment and implementation techniques used to obtain this speedup. The distributed processing environment can also be applied to many other CAD problems
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:9
,
Issue:
6
)
Date of Publication: Jun 1990
- Page(s):
- 655 - 664
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 3721467
- Digital Object Identifier :
- 10.1109/43.55195
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jun 1990
- Sponsored by :
- IEEE Council on Electronic Design Automation
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