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Estimation of maximum currents in MOS IC logic circuits

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2 Author(s)
Chowdhury, S. ; Dept. of Electr. & Comput. Eng., Univ. of Iowa, Iowa City, IA, USA ; Barkatullah, J.S.

The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a macro-cell (macro) in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs. The macro currents are used to estimate the maximum currents in the segments of power (ground) distribution systems. Some of the algorithms provide tradeoff between runtime and quality of solutions. Experimental results are included

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 6 )