Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 5:00 PM ET (12:00 - 21:00 UTC). We apologize for the inconvenience.
By Topic

A 5 Gbps 0.13 \mu m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ahmadi, M.R. ; Adv. Micro Devices (AMD), Boxborough, MA, USA ; Amirkhany, A. ; Harjani, R.

This paper presents a pilot-based clock and data recovery (CDR) technique for high-speed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection-locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential receiver fabricated in a 0.13 μm IBM CMOS technology. The clock and data recovery circuit implementation has an area of 0.171 mm2 and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-to-peak and RMS jitter at 5 Gbps are less than 10 ps (5%UI) and 1.6 ps (0.8%UI), respectively with an effective CDR loop bandwidth of approximately 28 MHz at a bit-error rate (BER) of 10-12 . The proposed technique simplifies the CDR design and provides data and inter-symbol interference (ISI) independent performance with a small ≈5% pilot voltage overhead to the transmitted data signal.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 8 )