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We present an all-digital measurement circuit that enables wafer-level test and characterization of phase-locked loop (PLL) response. Through modifications only in the PLL feedback divider state machine, this technique facilitates accurate estimation of PLL frequency-domain closed-loop bandwidth and gain peaking by respectively measuring the time-domain crossover time and maximum overshoot of phase error to a self-induced phase step in the feedback clock. These transient measurements are related back to bandwidth and peaking through the proportionality relationships of crossover time to reciprocal bandwidth and maximum overshoot to peaking. The design-for-test circuit can be used to generate a transient plot of step response, measure static phase error, and observe phase-lock status. We report silicon results from two demonstration vehicles built in a 45-nm SOI-CMOS logic technology for high-performance microprocessors.